Heretofore, a multilayer wiring board has been adopted by integrally laminating a prepreg or a resin film on a wired inner layer material, and a metal foil as an upper layer thereof, creating a hole for interlayer connection by laser to form a base electroless plating layer, and then filling in the hole for interlayer connection with an electrolytic plating layer formed by using an electrolytic filling plating solution (hereinafter, also simply referred to as an “electrolytic filling plating layer”).
In this respect, particularly, for a hole for interlayer connection whose via diameter is nearly equal, i.e., aspect ratio is approximately 1, or more compared with the insulating layer thickness, there is a tendency that a plating void (hereinafter, also simply referred to as a “void”) easily occurs in the inside of the via. A multilayer wiring board to which an electrolytic plating method that is carried out for a long time at a low electric current density or an electrolytic plating method with an electric current density controlled in stages is applied has been proposed as a method for suppressing such a plating void (Patent Literature 1). Furthermore, a multilayer wiring board to which a method of carrying out the formation of an electrolytic plating layer in two divided portions is applied from the viewpoint of surface smoothness has been proposed as to the filling-in of the hole for interlayer connection (Patent Literature 2).